Analog/digital converters (ADCs) are key chips, particularly in modern broadband transceivers, for example for the mobile radio standards 802.11a/b (wireless LAN) or UMTS. In this case, analog/digital converters form the interface between the digital and the analog signal processing. The converters convert an analog input signal into a number which is proportional thereto, which is output as a digital signal. The digital signal is frequently a serial sequence of a number of individual binary states, with the assembled binary value of the sequence representing the proportional number. The number of bits per represented digital signal is a measure of the latter's accuracy. An analog/digital converter having an accuracy of 8 bits thus converts an analog input signal into a binary sequence comprising a total of 8 bits. In principle, an analog input range for the analog/digital converter is therefore split into a total of 256 subranges, with each individual subrange, starting at the lowest, being assigned a binary sequence of numbers comprising 8 bits. By way of example, the lowest subrange is thus assigned the decimal value 0, and the highest subrange is assigned the decimal value 255 or, in binary, 11111111. The analog/digital converter now converts the amplitude of the input signal, which is in one of the 256 subranges, into the associated decimal value.
Analog/digital converters are implemented in various ways. One option is to use successive approximation. In this case, the analog/digital converter performs a plurality of individual approximation steps, with a digital subvalue being ascertained in each step and being used to form the digital total value. The number of approximation steps corresponds to the binary accuracy of the digital value. Tietze/Schenk, “Halbleiterschaltungstechnik” [Semiconductor circuitry], 12th edition, Springer 2002, pp. 1009 to 1011 describes a simple example of such an approximation.
One variation of the method described therein compares an input signal or, expediently, the amplitude or the level of an input signal in an approximation step not with a reference voltage, but rather with two reference voltages or with two reference potentials. This ascertains whether the voltage of the input signal is above or below the two reference voltages or whether it is between the two. The input range containing the input signal is therefore divided into a total of three subranges by the two reference voltages in this approximation step, and the comparison ascertains which of these three subranges contains the voltage of the input signal. On the basis of this result, a new signal is produced which is used as an input signal for the subsequent approximation step. In addition, a control signal is generated from the result. This control signal is clearly associated with the range into which the voltage of the input signal has been placed. The control signal is used for forming the digital output value of the analog/digital converter.
Analog/digital converters with successive approximation are expediently designed for a clocked mode of operation and with sample-and-hold circuits. Frequently, each individual approximation step is produced by an individual subcircuit in the analog/digital converter. During a sampling phase, the input signals are sampled in the individual stages of the analog/digital converter. In a holding phase which follows the sampling phase, signal processing takes place, which, inter alia, produces the control signal and also the new signal for the subsequent approximation step or the subsequent stage of the analog/digital converter.
Modern analog/digital converters with a resolution of 10 bits, a bandwidth of 20 MHz and a typical sampling rate of 80 MHz now draw a current of only 23 mA at a supply voltage of 1.5 V. However, the trend toward smaller CMOS technologies between, nowadays, 0.13 mm and 0.08 mm in the near future requires new circuits and extensions in the algorithm in order to prevent the current draw from rising again. In this case, the service life of mobile appliances would also be extended, in particular.
In order to reduce the amount of current draw in analog/digital converters, the printed document “A 250 mW, 8-bit, 52 M Samples/s parallel-pipelined A/D converter with reduced number of amplifiers”, IEEE, Journal of Solid State Circuits, vol. 32, No. 3, March 1997 by Nagara et al., and the document “A 69 mW 10b 80 MS/s Pipeline CMOS ADC”, ISSCC 2003/Session 18/Niquist A/D converters/paper 18.4 by Min et al. have described an analog/digital converter in which two successive stages of the analog/digital converter respectively share one amplifier. This allows a more significant reduction in both chip area and current draw. However, a drawback of these circuits is that they are not always able to meet the rising demands for bandwidth and sampling rate. Particularly at high clock rates, the switching times are so short that the switches required therefor can be implemented only with a high level of complexity. In addition, the supply voltage for the exemplary embodiments illustrated needs to be chosen to be very high.